Seats are limited. Sign up by 5 June 2026, 6pm (Nzst). 
Please contact Filip Zganec (filip.zganec@rohde-schwarz.com) for registration queries.

As data rates push into the GHz range and power densities continue to rise, modern hardware design demands a more integrated approach. Tighter timing margins, increased noise sensitivity, and complex test environments make accurate signal characterization increasingly challenging.

This seminar brings together key measurement and design strategies to help engineers confidently validate performance.

Join us in New Zealand for expert-led sessions and live demonstrations focused on solving real-world test and measurement challenges — from signal integrity to power electronics and EMC.

 

Catch us in two cities:

1. Auckland - Thursday, 11 June 2026, 9.30am - 4pm

• Venue: University of Auckland, Level 1, Building 405, 5/7 Grafton Road, Auckland CBD, Auckland 101

 

2. Christchurch - Tuesday, 16 June 2026, 9.30am - 4pm

• Venue: University of Canterbury, John Britten Conference Foyer 102, 69 Creyke Road, Ilam, Christchurch 8041

 

You will learn about:

• Signal integrity & debug
  Master eye analysis and advanced debugging to isolate physical layer issues in high-speed links.
• Decoding jitter & noise
  Analyze the critical relationship between signal and power integrity through comprehensive jitter and noise decomposition.
• Precision de-embedding
  Learn how to effectively "remove" the test fixture using VNAs and oscilloscopes to ensure compliance and accuracy.
• Power & EMC mastery
  Navigate the complexities of power sequencing, the fast-switching noise of WBG devices, and the path to EMC compliance.